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? semiconductor components industries, llc, 2013 may, 2013 ? rev. 13 1 publication order number: mc74hc161a/d mc74hc161a, mc74hc163a presettable counters high ? performance silicon ? gate cmos the mc74hc161a and hc163a are identical in pinout to the ls161 and ls163. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with lsttl outputs. the hc161a and hc163a are programmable 4 ? bit binary counters with asynchronous and synchronous reset, respectively. features ? output drive capability: 10 lsttl loads ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 2.0 to 6.0 v ? low input current: 1.0 a ? high noise immunity characteristic of cmos devices ? in compliance with the requirements defined by jedec standard no. 7a ? chip complexity: 192 fets or 48 equivalent gates ? these are pb ? free devices *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. http://onsemi.com marking diagrams soic ? 16 d suffix case 751b tssop ? 16 dt suffix case 948f 1 16 1 16 1 16 hc16xag awlyww hc 16xa alyw 1 16 x = 1 or 3 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g or = pb ? free package see detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. ordering information (note: microdot may be in either location)
mc74hc161a, mc74hc163a http://onsemi.com 2 inputs output clock reset* load enable p enable t q l x x x reset h l x x load preset data h h h h count h h l x no count h h x l no count function table *hc163a only. hc161a is an asynchronous reset device h = high level, l = low level, x = don?t care figure 1. pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 reset p0 clock gnd q1 q0 ripple carry out v cc p1 p2 p3 enable p q2 q3 enable t load figure 2. logic diagram pin 16 = v cc pin 8 = gnd 11 12 13 14 q0 q1 q2 q3 15 ripple carry out bcd or binary output 3 4 5 6 p0 p1 p2 p3 2 clock reset load enable p enable t count enables preset data inputs 1 9 7 10 device/mode table device count mode reset mode hc161a binary asynchronous hc163a binary synchronous
mc74hc161a, mc74hc163a http://onsemi.com 3 maximum ratings symbol parameter value unit v cc dc supply voltage 0.5 to 7.0 v v i dc input voltage 0.5 to v cc 0.5 v v o dc output voltage (note 1) 0.5 v o v cc 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 25 ma i o dc output sink current 25 ma i cc dc supply current per supply pin 50 ma i gnd dc ground current per ground pin 50 ma t stg storage temperature range 65 to 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias 150 c ja thermal resistance soic tssop 112 148 c/w p d power dissipation in still air at 85 c soic tssop 500 450 mw msl moisture sensitivity level 1 f r flammability rating oxygen index: 30% ? 35% ul 94 v ? 0 @ 0.125 in v esd esd withstand voltage human body model (note 2) machine model (note 3) 2000 200 v i latchup latchup performance above v cc and below gnd at 85 c (note 4) 300 ma stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. i o absolute maximum rating must be observed. 2. tested to eia/jesd22 ? a114 ? a. 3. tested to eia/jesd22 ? a115 ? a. 4. tested to eia/jesd78. recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types 55 125 c t r , t f input rise and fall time (figure 4) v cc = 2.0 v v cc = 3.0 v v cc = 4.5 v v cc = 6.0 v 0 0 0 0 1000 600 500 400 ns 5. unused inputs may not be left open. all inputs must be tied to a high ? or low ? logic input voltage level.
mc74hc161a, mc74hc163a http://onsemi.com 4 dc electrical characteristics (voltages referenced to gnd) symbol parameter test conditions v cc v guaranteed limit unit ?55 to 25 c 85 c 125 c v ih minimum high ? level input voltage v out = 0.1 v or v cc ? 0.1 v |i out | 20 a 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 v v il maximum low ? level input voltage v out = 0.1 v or v cc ? 0.1 v |i out | 20 a 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 v v oh minimum high ? level output voltage v in = v ih or v il |i out | 20 a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in = v ih or v il |i out | 3.6 ma |i out | 4.0 ma |i out | 5.2 ma 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.2 3.7 5.2 v ol maximum low ? level output voltage v in = v ih or v il |i out | 20 a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v ih or v il |i out | 3.6 ma |i out | 4.0 ma |i out | 5.2 ma 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.4 0.4 0.4 i in maximum input leakage current v in = v cc or gnd 6.0 0.1 1.0 1.0 a i cc maximum quiescent supply current v in = v cc or gnd i out = 0 a 6.0 4.0 40 160 a
mc74hc161a, mc74hc163a http://onsemi.com 5 ac electrical characteristics (c l = 50 pf, input t r = t f = 6.0 ns) symbol parameter figure v cc v guaranteed limit unit ? 55 to 25 c 85 c 125 c f max maximum clock frequency (50% duty cycle) (note 6) 4, 10 2.0 3.0 4.5 6.0 6 15 30 35 5 12 24 28 4 10 20 24 mhz t plh maximum propagation delay, clock to q 4, 10 2.0 3.0 4.5 6.0 120 75 20 16 160 120 23 20 200 150 28 22 ns t phl 4, 10 2.0 3.0 4.5 6.0 145 100 22 18 185 135 25 20 220 150 30 23 ns t phl maximum propagation delay, reset to q (hc161a only) 5, 10 2.0 3.0 4.5 6.0 145 100 20 17 185 135 22 19 220 150 25 21 ns t plh maximum propagation delay, enable t to ripple carry out 6, 10 2.0 3.0 4.5 6.0 110 60 16 14 150 115 18 15 190 140 20 17 ns t phl 6, 10 2.0 3.0 4.5 6.0 135 100 18 15 175 130 20 16 210 160 22 20 ns t plh maximum propagation delay, clock to ripple carry out 4, 10 2.0 3.0 4.5 6.0 120 75 22 18 160 135 27 22 200 150 30 25 ns t phl 4, 10 2.0 3.0 4.5 6.0 145 100 22 20 185 135 28 24 220 150 35 28 ns t phl maximum propagation delay, reset to ripple carry out (hc161a only) 5, 10 2.0 3.0 4.5 6.0 155 120 22 18 190 140 26 22 230 155 30 25 ns t tlh , t thl maximum output transition time, any output 5, 10 2.0 3.0 4.5 6.0 75 30 15 13 95 40 19 16 110 55 22 19 ns c in maximum input capacitance 4, 10 ? 10 10 10 pf 6. applies to noncascaded/nonsynchronous clocked configurations only with synchronously cascaded counters. (1) clock to ripple c arry out propagation delays. (2) enable t or enable p to clock setup times and (3) clock to enable t or enable p hold times determine f max . however, if ripple carry out of each stage is tied to the clock of the next stage (nonsynchronously clocked) the f max in the table above is applicable. see applications information in this data sheet. c pd power dissipation capacitance (per gate) (note 7) typical @ 25 c, v cc = 5.0 v pf 45 7. used to determine the no ? load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc .
mc74hc161a, mc74hc163a http://onsemi.com 6 timing requirements (c l = 50 pf, input t r = t f = 6.0 ns) symbol parameter figure v cc v guaranteed limit unit ? 55 to 25 c 85 c 125 c t su minimum setup time, preset data inputs to clock 8 2.0 3.0 4.5 6.0 40 20 15 12 60 30 20 18 80 40 30 20 ns t su minimum setup time, load to clock 8 2.0 3.0 4.5 6.0 60 25 15 12 75 30 20 18 90 40 30 20 ns t su minimum setup time, reset to clock (hc163a only) 7 2.0 3.0 4.5 6.0 60 25 20 17 75 30 25 23 90 40 35 25 ns t su minimum setup time, enable t or enable p to clock 9 2.0 3.0 4.5 6.0 80 35 20 17 95 40 25 23 110 50 35 25 ns t h minimum hold time, clock to load or preset data inputs 8 2.0 3.0 4.5 6.0 3 3 3 3 3 3 3 3 3 3 3 3 ns t h minimum hold time, clock to reset (hc163a only) 7 2.0 3.0 4.5 6.0 3 3 3 3 3 3 3 3 3 3 3 3 ns t h minimum hold time, clock to enable t or enable p 9 2.0 3.0 4.5 6.0 3 3 3 3 3 3 3 3 3 3 3 3 ns t rec minimum recovery time, reset inactive to clock (hc161a only) 5 2.0 3.0 4.5 6.0 80 35 15 12 95 40 20 17 110 50 26 23 ns t rec minimum recovery time, load inactive to clock 8 2.0 3.0 4.5 6.0 80 35 15 12 95 40 20 17 110 50 26 23 ns t w minimum pulse width, clock 4 2.0 3.0 4.5 6.0 60 25 12 10 75 30 15 13 90 40 18 15 ns t w minimum pulse width, reset (hc161a only) 5 2.0 3.0 4.5 6.0 60 25 12 10 75 30 15 13 90 40 18 15 ns t r , t f maximum input rise and fall times 2.0 3.0 4.5 6.0 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns
mc74hc161a, mc74hc163a http://onsemi.com 7 function description the hc161a/163a are programmable 4 ? bit synchronous counters that feature parallel load, synchronous or asynchronous reset, a carry output for cascading, and count ? enable controls. the hc161a and hc163a are binary counters with asynchronous reset and synchronous reset, respectively. inputs clock (pin 2) the internal flip ? flops toggle and the output count advances with the rising edge of the clock input. in addition, control functions, such as resetting and loading, occur with the rising edge of the clock input. preset data inputs p0, p1, p2, p3 (pins 3, 4, 5, 6) these are the data inputs for programmable counting. data on these pins may be synchronously loaded into the internal flip ? flops and appear at the counter outputs. p0 (pin 3) is the least ? significant bit and p3 (pin 6) is the most ? significant bit. outputs q0, q1, q2, q3 (pins 14, 13, 12, 11) these are the counter outputs. q0 (pin 14) is the least ? significant bit and q3 (pin 11) is the most ? significant bit. ripple carry out (pin 15) when the counter is in its maximum state, 1111, this output goes high, providing an external look ? ahead carry pulse that may be used to enable successive cascaded counters. ripple carry out remains high only during the maximum count state. the logic equation for this output is: ripple carry out = enable t ? q0 ? q1 ? q2 ? q3 output state diagrams 01234 5 6 7 8 9 10 11 12 13 14 15 figure 3. binary counters control functions resetting a low level on the reset pin (pin 1) resets the internal flip ? flops and sets the outputs (q0 through q3) to a low level. the hc161a resets asynchronously , and the hc163a resets with the rising edge of the clock input (synchronous reset). loading with the rising edge of the clock, a low level on load (pin 9) loads the data from the preset data input pins (p0, p1, p2, p3) into the internal flip ? flops and onto the output pins, q0 through q3. the count function is disabled as long as load is low. count enable/disable these devices have two count ? enable control pins: enable p (pin 7) and enable t (pin 10). the devices count when these two pins and the load pin are high. the logic equation is: count enable = enable p ? enable t ? load the count is either enabled or disabled by the control inputs according to table 1. in general, enable p is a count ? enable control: enable t is both a count ? enable and a ripple ? carry output control. table 1. count enable/disable control inputs result at outputs load enable p enable t q0 ? q3 ripple carry out h h h count high when q0 ? q3 are maximum* l h h no count x l h no count high when q0 ? q3 are maximum* x x l no count l *q0 through q3 are maximum when q3, q2, q1, q0 = 1111.
mc74hc161a, mc74hc163a http://onsemi.com 8 figure 4. figure 5. figure 6. figure 7. hc163a only figure 8. figure 9. test circuit figure 10. t r t f v cc gnd t thl t tlh any output 90% 50% 10% 90% 50% 10% clock t plh t phl 50% t phl v cc gnd v cc gnd any output clock reset 50% 50% t rec t r t f v cc gnd t phl t plh 90% 50% 10% 90% 50% 10% t thl t tlh enable t ripple carry out clock reset 50% t su v cc gnd 50% inputs p0, p1, p2, p3 50% v cc gnd v cc gnd gnd 50% 50% load clock v cc gnd v cc gnd enable t or enable p 50% 50% clock *includes all probe and jig capacitance c l * test point device under test output v cc t w 1/fmax t w t h valid t su t h t su t h t rec valid t su t h switching waveforms
mc74hc161a, mc74hc163a http://onsemi.com 9 p0 p1 p2 p3 enable p enable t reset t0 r c c load load p0 q0 q0 q1 q2 q3 ripple carry out v cc = pin 16 gnd = pin 8 14 the flip ? flops shown in the circuit diagrams are toggle ? enable flip ? flops. a toggle ? enable flip ? flop is a combination of a d flip ? flop and a t flip ? flop. when loading data from preset inputs p0, p1, p2, and p3, the load signal is used to disable the toggle input (tn) of the flip ? flop. the logic level at the pn input is then clocked to the q output of the flip ? flop on the next rising edge of the clock. a logic zero on the reset device input forces the internal clock (c) high and resets the q output of the flip ? flop low. q0 q1 q1 q2 q2 q3 t1 r c c load load p1 t2 r c c load load p2 t3 r c c load load p3 13 12 11 15 3 4 5 6 7 10 1 figure 11. 4 ? bit binary counter with asynchronous reset (mc74hc161a) r c c load load clock load 9 2
mc74hc161a, mc74hc163a http://onsemi.com 10 reset (hc161a) reset (hc163a) load p0 p1 p2 p3 clock (hc161a) clock (hc163a) enable p enable t q0 q1 q2 q3 ripple carry out (asynchronous) (synchronous) 12 13 14 15 0 1 2 reset load count enables outputs preset data inputs inhibit count figure 12. timing diagram sequence illustrated in waveforms: 1. reset outputs to zero. 2. preset to binary twelve. 3. count to thirteen, fourteen, fifteen, zero, one and two. 4. inhibit.
mc74hc161a, mc74hc163a http://onsemi.com 11 p0 p1 p2 p3 enable p enable t reset t0 r c c load load p0 q0 q0 q1 q2 q3 ripple carry out v cc = pin 16 gnd = pin 8 14 the flip ? flops shown in the circuit diagrams are toggle ? enable flip ? flops. a toggle ? enable flip ? flop is a combination of a d flip ? flop and a t flip ? flop. when loading data from preset inputs p0, p1, p2, and p3, the load signal is used to disable the toggle input (tn) of the flip ? flop. the logic level at the pn input is then clocked to the q output of the flip ? flop on the next rising edge of the clock. a logic zero on the reset device input forces the internal clock (c) high and resets the q output of the flip ? flop low. q0 q1 q1 q2 q2 q3 t1 r c c load load p1 t2 r c c load load p2 t3 r c c load load p3 13 12 11 15 3 4 5 6 7 10 1 9 2 r c c load load clock load figure 13. 4 ? bit binary counter with synchronous reset (mc74hc163a)
mc74hc161a, mc74hc163a http://onsemi.com 12 inputs outputs to more load h = count l = disable h = count l = disable reset clock load p0 p1 p2 p3 enable p enable t clock rq0q1q2q3 ripple carry out load reset clock enable p enable t typical applications cascading note: when used in these cascaded configurations the clock f max guaranteed limits may not apply. actual performance will depend on number of stages. this limitation is due to set up times between enable (port) and clock. outputs outputs figure 14. n ? bit synchronous counters figure 15. nibble ripple counter significant stages inputs inputs load p0 p1 p2 p3 enable p enable t clock rq0q1q2q3 ripple carry out load p0 p1 p2 p3 enable p enable t clock rq0q1q2q3 ripple carry out load p0 p1 p2 p3 enable p enable t clock rq0q1q2q3 ripple carry out load p0 p1 p2 p3 enable p enable t clock rq0q1q2q3 ripple carry out load p0 p1 p2 p3 enable p enable t clock rq0q1q2q3 ripple carry out to more significant stages inputs outputs outputs outputs inputs inputs
mc74hc161a, mc74hc163a http://onsemi.com 13 figure 16. modulo ? 5 counter hc163a typical applications varying the modulus output optional buffer for noise rejection other inputs reset hc163a q0 q1 q2 q3 figure 17. modulo ? 11 counter output optional buffer for noise rejection other inputs q0 q1 q2 q3 reset the hc163a facilitates designing counters of any modulus with minimal external logic. the output is glitch ? free due to the synchronous reset. ordering information device package shipping ? mc74hc161adtg tssop ? 16 (pb ? free) 96 units / tube mc74hc163adtg tssop ? 16 (pb ? free) 96 units / tube MC74HC161ADG soic ? 16 (pb ? free) 48 units / rail mc74hc161adr2g soic ? 16 (pb ? free) 2500 units / tape & reel mc74hc161adtr2g tssop ? 16* 2500 units / tape & reel mc74hc163adg soic ? 16 (pb ? free) 48 units / rail mc74hc163adr2g soic ? 16 (pb ? free) 2500 units / tape & reel mc74hc163adtr2g tssop ? 16* 2500 units / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *this package is inherently pb ? free.
mc74hc161a, mc74hc163a http://onsemi.com 14 package dimensions tssop ? 16 dt suffix case 948f ? 01 issue b ??? ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . section n ? n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g ? u ? s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ? t ? ? v ? ? w ? 0.25 (0.010) 16x ref k n n 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint
mc74hc161a, mc74hc163a http://onsemi.com 15 package dimensions soic ? 16 d suffix case 751b ? 05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ? b ? ? a ? m 0.25 (0.010) b s ? t ? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint 16 89 8x on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 mc74hc161a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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